The present invention relates generally to a semiconductor package, and more particularly, to a semiconductor package which can be mounted with a plurality of semiconductor chips and can prevent the manufacturing yield from decreasing due to the defects of semiconductor chips.
In the semiconductor industry, packaging technology is continuously being developed to meet demands for miniaturization and mounting efficiency. Recently, as electric and electronic is products trend toward miniaturization and high performance, various techniques for stacking have been researched.
The term “stack” when referred to in the semiconductor industry means to vertically pile at least two chips or packages. By this stack technique, in the case of a memory device, it is possible to realize a product having a memory capacity at least two times greater than that obtainable through semiconductor integration processes, and mounting area utilization efficiency can be improved.
However, in the conventional semiconductor package (hereinafter referred to as a “stack package”) manufactured using the stack technique, since signal connections to respective semiconductor chips are realized through metal wires, disadvantages are caused in that the operation speed of each semiconductor chip is diminished. Also, since an additional area for wire bonding is required in a substrate, the size of the package increases. In addition, a gap is required to bond wires to the bonding pads of the respective semiconductor chips causing an increased overall height.
In order to overcome the above disadvantages of the conventional stack package, a stack package structure using through-silicon vias (hereinafter referred to as “through-electrodes”) has been suggested.
The stack package using through-electrodes is realized by forming through-electrodes in semiconductor chips, and then stacking a plurality of the semiconductor chips formed with the through-electrodes in a manner such that the through-electrodes of the respective semiconductor chips are electrically connected to one another.
The stack package using the through-electrodes provides advantages in that, since an additional area for forming electrical connections is not required in a substrate, mounting efficiency can be improved. Also, since a gap for wire bonding is not required between the semiconductor chips, the overall height of the semiconductor package can be decreased in comparison to the conventional art. In addition, because a signal connection length to each semiconductor chip is shortened, the operation speed of each semiconductor chip can be increased, whereby high speed operation of the semiconductor chip can be ensured.
Moreover, in the stack package using the through-electrodes, since the plurality of semiconductor chips can be mounted in one package, a multi-chip package having high performance and high capacity can be realized.
Nevertheless, in a conventional stack package using through-electrodes, if defects occur in even one of the stacked semiconductor chips, all of the stacked semiconductor chips must be discarded, whereby the manufacturing yield decreases. Due to this fact, in the conventional stack package using the through-electrodes, it is required that special attention be paid so that is defects are not caused in the individual semiconductor chips, whereby the manufacturing cost increases.